• Research Assistant: SI Lab


    September 2017, I rejoined "SI Lab" as a Research Associate. Taking advantage of my prior assistantship experiences and the results gained from my dissertation, we are focused on developing a neural network based DVFS network to efficiently utilize energy (or timing) budget. We are also thinking of novel solutions to dynamically absorb the timing errors raised from misestimations in the neural network. We use the information attained from the instructions in the execution unit to predict the execution time, and accordingly, setting the clock frequency (or power supply) values. A recovery mechanism is also exploited to prevent the system from losing its correct state, and to guarantee the correctness of computations.

  • Research Assistant: ESL Tools & Methodologies Lab


    From May 2016 to May 2017, I was a part of "ESL Tools & Methodologies Lab" as a Research Assistant (RA). Initially, I was an assist to Ms. Hanieh Hashemi on her M.S. thesis. At that time, we were focused on "Better than Worst-Case Design" techniques, and I had to gather testbenches, extract the customized-attributes during the execution of the processor, process the raw data, and interpret the results in the intended regime. The result of our co-operation is presented in the article "Early Prediction of Timing Critical Instructions in Pipeline Processor," presented in Baltic Electronics Conference; Tallinn, Estonia; 2016. After Hanieh's defence, I took the responsibility to continue BTWC techniques research as a part of my bachelors' degree dissertation: "FPGA Realization of Better than Worst-Case Design Techniques." In my dissertation, I was trying to synthesize our previously introduced techniques on FPGAs in order to verify their applicability and efficiency, as well as proposing better techniques. I defended my dissertation in March 2017 with grade: 20 (out of 20).

  • Research Assistant: Silicon Intelligence & VLSI Signal Processing Lab

    I was an RA in the "SI lab" between March 2015 and June 2016. During my presence in SI lab, I was an assist to Mr. Iraj Moghaddas on his PhD thesis by gathering testbenches, extracting the customized-attributes during the execution of the processor, and processing the raw data for further interpretation. We were focused on analyzing CPU loads, and based on the stress applied to each net in the design, we were trying to predict the ageing rate of the processor. Our work resulted in a journal article: "Fine-Grained Ageing Rate Prediction for Embedded Cores Using Instruction-Level Stress Monitoring," which is intended to be published in IEEE Transactions on Computer-Aided Design (TCAD).